View KS0093_851390.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

26 com / 80 seg driver & controller for stn lcd nov. 1999. ver. 0.4 prepared by : won- sik, kang k2w3@samsung.co.kr KS0093 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.

26 com / 80 seg driver & controller for stn lcd KS0093 1 KS0093 specification revision history version content date 0.0 original jun. 1998 0.1 miss typed contents changed jan.1999 0.2 resetb pin v il ,v ih added mar.1999 0.3 vdd change (2.4v~5.5v -> 2.4v~3.6v) nov. 199 9 0.4 vdd change (2.4v~3.6v -> 2.4v~5.5 v) dec . 199 9
KS0093 26 com / 80 seg driver & controller for stn lcd 2 contents introduction ................................ ................................ ................................ ................................ .......... 1 features ................................ ................................ ................................ ................................ ................. 1 block diagram ................................ ................................ ................................ ................................ ...... 3 pad configuration ................................ ................................ ................................ ............................... 4 pad center coordinates ................................ ................................ ................................ ................... 5 pin description ................................ ................................ ................................ ................................ ...... 6 power supply ................................ ................................ ................................ ................................ . 6 lcd driver supply ................................ ................................ ................................ ......................... 6 system control ................................ ................................ ................................ ............................. 7 mpu interface ................................ ................................ ................................ ................................ 7 lcd driver outputs ................................ ................................ ................................ ...................... 8 test ................................ ................................ ................................ ................................ .................... 8 function description ................................ ................................ ................................ .......................... 9 system interface ................................ ................................ ................................ .......................... 9 address counter (ac) ................................ ................................ ................................ ................ 13 display data ram (ddram) ................................ ................................ ................................ ......... 13 character generator rom (cgrom) ................................ ................................ ..................... 13 character generator ram (cgram) ................................ ................................ ..................... 15 segment icon ram (iconram) ................................ ................................ ................................ .... 17 low power consumption mode ................................ ................................ .............................. 18 lcd driver circuit ................................ ................................ ................................ ....................... 18 instruction description ................................ ................................ ................................ .................. 19 initializing & power save mode setup ................................ ................................ ......................... 29 hardware reset ................................ ................................ ................................ .......................... 29 initializing and power save setup ................................ ................................ ......................... 30 lcd driving power supply circuit ................................ ................................ ................................ 33 voltage converter ................................ ................................ ................................ .................... 34 voltage regulator ................................ ................................ ................................ .................... 35 electronic contrast control (32 steps) ................................ ................................ ........... 36 voltage generator circuit ................................ ................................ ................................ .... 38 mpu interface ................................ ................................ ................................ ................................ ...... 39 application information for lcd panel ................................ ................................ .................... 41 frame frequency ................................ ................................ ................................ ............................... 43 maximum absolute ratings ................................ ................................ ................................ ............. 44 electrical characteristics ................................ ................................ ................................ .......... 45 dc characteristics ................................ ................................ ................................ .................... 45 ac characteristics ................................ ................................ ................................ .................... 47
26 com / 80 seg driver & controller for stn lcd KS0093 1 introduction the KS0093 is an lcd driver and controller lsi for liquid crystal dot matrix character display systems. it can display 2 or 3 lines of 16 characters with 5 x 8 dots format. it is capable of interfacing various microprocessors, supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. voltage converter, oscillator, voltage regulator, voltage follower and bias circuit are built in the ic. the double height character mode and line vertical scroll function s are supported. features driver outputs - common o utputs: 26 common - segment o utputs: 80 segment applicable panel size font display duty contents of outputs 2 - line x 16 characters 1 / 17 2 x 16 characters + 80 icons 5 x 8 3 - line x 16 characters 1 / 25 3 x 16 characters + 80 icons internal memory - character generator rom (cgrom): 10,240 bits (256 characters x 5 x 8 dots) - character generator ram (cgram): 320 bits (8 characters x 5 x 8 dots) - display data ram (ddram): 512 bits (16 characters x 4 lines) - segment icon ram (iconram): 80 bits (80 icons) mpu interface - no busy mpu interface (no busy check or no execution waiting time) - 8-bit parallel interface mode: 68-series and 80-series are available. - 4-bit parallel interface mode: 68-series and 80-series are available. - serial interface mode: 4 pins clock synchronized serial interface function set - various instruction set: display control, power save, power control, etc. - com / seg bi-directional (4-type lcd application available) - h/w reset (resetb) built-in analog circuit - internal rc oscillator circuit or external clock - electronic volume for contrast control (32 steps) - voltage converter / voltage regulator / voltage follower & bias circuit low power operation - sleep mode operation (5 m a max.) - normal mode operation (80 m a max.)
KS0093 26 com / 80 seg driver & controller for stn lcd 2 operating voltage range - power supply voltage (v dd ): 2.4v ~ 5.5v - lcd driving voltage (v lcd = v0 - v ss ): 6.0v max. package type - gold bumped c hip or tcp
26 com / 80 seg driver & controller for stn lcd KS0093 3 block diagram parallel interface 4 bit/8 bit serial interface input buffer instruction register (ir) 8 instruction decoder address counter display data ram (ddram) 512 bits data register (dr) 8 icon ram 80 bits character generator ram (cgram) 320 bits character generator rom (cgrom) 10240 bits cursor and blink controlle r common driver 25 bits shift register segment driver 80 bits latch circuit 80 bits shift register lcd driver voltage selector segment data conversion lcd driving power circuit voltage converter voltage regulator voltage follower & bias resistor timing generator oscillator seg1- seg80 m i csb rs rw_wr e_rd db7 (si) db6 (scl) db5- db4 db3- db0 resetb ps if cap1+ cap1- cap2+ cap2- vout v0 vext ref vr v1 v2 v3 v4 dirs ck com1- com24 com i1 com i2 v dd gnd 7 8 8 5 5 8 8 data output register (or) 8 5 figure 1. block diagram
KS0093 26 com / 80 seg driver & controller for stn lcd 4 pad configuration ............................ ........................... ... .. ... x y (0,0) dummy pad pad 1 73 74 86 87 167 179 166 figure 2. pad configuration table 1 . KS0093 pad dimensions size item pad no. x y unit chip size - 7020 1620 1 ~ 73 90 pad pitch 74 ~ 179 80 1 ~ 73 60 100 74 ~ 86 100 50 87 ~ 166 50 100 bumped pad size 167 ~ 179 100 50 bumped pad height all pad 17 m m cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (-3065, - 445) 30 m m 30 m m 30 m m (-2965, - 405) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-3440, +740) (+3440, +740) 42 m m 108 m m
26 com / 80 seg driver & controller for stn lcd KS0093 5 pad center coordinates table 2. p ad center coordinates [unit: m m] pad no. pad n ame x y pad no. pad name x y pad no. pad name x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 dummy dummy dummy dummy dummy rs vss rw_wr vdd e_rd csb db7 db6 db5 db4 db3 db2 db1 db0 vdd vdd vdd vss vss vss v4 v4 v3 v3 v2 v2 v1 v1 v0 v0 v0 v0 vr vr vout vout cap2- cap2- cap2+ cap2+ cap1- cap1- cap1+ cap1+ vext vss vss vss ref dirs vdd vdd vdd ck vss -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620 -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 - 270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 ps vdd if vss mi vdd resetb test dummy dummy dummy dummy dummy comi1 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 2160 2250 2340 2430 2520 2610 2700 2790 2880 2970 3060 3150 3240 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3160 3080 3000 2920 2840 2760 2680 2600 2520 2440 2360 2280 2200 2120 2040 1960 1880 1800 1720 1640 1560 1480 1400 1320 1240 1160 1080 1000 920 840 760 680 600 520 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -520 -440 -360 -280 -200 -120 -40 40 120 200 280 360 440 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 comi2 com24 com23 com22 com21 com16 com15 com14 com13 com12 com11 com10 com9 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520 -600 -680 -760 -840 -920 -1000 -1080 -1160 -1240 -1320 -1400 -1480 -1560 -1640 -1720 -1800 -1880 -1960 -2040 -2120 -2200 -2280 -2360 -2440 -2520 -2600 -2680 -2760 -2840 -2920 -3000 -3080 -3160 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520
KS0093 26 com / 80 seg driver & controller for stn lcd 6 pin description power s upply table 3. pin description name i/o description v dd power supply connect to mpu power supply pin . v ss power 0v (gnd) bias voltage level for lcd driving voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the built-in power circuit is active and internal 1/5 bias resistors are used. lcd b ias v1 v2 v3 v4 1/5 b ias (4/5) x v0 (3/5) x v0 (2/5) x v0 (1/5) x v0 when the built-in power circuit is active and internal 1/4 bias resistors are used. lcd b ias v1 v2 v3 v4 1/4 b ias (3/4) x v0 (2/4) x v0 (1/4) x v0 v0 v1 v2 v3 v4 i/o lcd d river s upply table 3. pin description (continued) name i/o description cap1+ o capacitor + connecting pin for the internal voltage converter cap1- o capacitor - connecting pin for the internal voltage converter cap2+ o capacitor + connecting pin for the internal voltage converter cap2- o capacitor - connecting pin for the internal voltage converter vout i/o dc/dc voltage converter output (7.2v) vr i voltage adjust pin this pin gives a voltage between v0 and v ss by resistance-division of voltage. vext i external reference voltage for internal regulator (instead of the internal v ref , 2v) ref = "low (v ss )": vext is not used (open) . ref = "high (v dd )": vext is reference input voltage of internal voltage regulator. ref i select the input voltage of internal voltage regulator ref = "low (v ss )": the input voltage of internal voltage regulator is the internal v ref (2v). ref = "high (v dd )": the input voltage of internal voltage regulator is the voltage of vext.
26 com / 80 seg driver & controller for stn lcd KS0093 7 system c ontrol table 3. pin description (continued) name i/o description ck i external clock input. it must be fixed to "high" or "low" when the internal oscillation circuit is used. in case of the external clock mode, ck is used as the clock and os bit should be off. mi i mpu interface selection input mi = "low": 80-series mpu mi = "high": 68-series mpu ps i parallel / serial selection input when ps = "low": serial mode when ps = "high": 4-bit / 8-bit bus mode if i interface data length selection pin for parallel data input when ps = "low" if = "low" or "high": serial interface mode when ps = high if = "low": 4-bit bus mode if = "high": 8-bit bus mode dirs i seg direction selection input when dirs = "low? seg1 ? seg2 ? seg79 ? seg80 when dirs = "high? seg80 ? seg79 ? seg2 ? seg1 mpu i nterface table 3. pin description (continued) name i/o description resetb i reset input KS0093 is initialized while resetb is low. csb i chip selection input KS0093 is selected while csb is low. rs i register selection input when rs = "low", instruction register when rs = "high", data register. rw_wr i in 80-series mpu interface mode this pin is connected to wr pin of mpu and is a active low write signal in 68-series mpu interface mode this pin is connected to r/w pin of mpu when rw_wr = "low", write mode when rw_wr = "high", read mode e_rd i in 80-series mpu interface mode this pin is connected to rd pin of mpu and is a active low read signal in 68-series mpu interface mode this pin is connected to e pin of mpu and enable read or write command according to rw_wr signal.
KS0093 26 com / 80 seg driver & controller for stn lcd 8 table 3. pin description (continued) name i/o description db0 ~ db3 db4 ~ db5 db6 (scl), db7 (si) i/o when 8-bit bus mode, used as bi-directional data bus db0 ~ db7 during 4-bit bus mode, only db4 ~ db7 are used. in this case db0 ~ db3 pins are not used. when serial mode, db6 (scl) is used as serial clock input pin and db7 (si) is used as serial data input pin. lcd d river o utputs table 3. pin description (continued) name i/o description com1 ~ com24 o common signal output for driving lcd comi1, comi2 o common signal output for icon display these are the same signal but the name is different. seg1 ~ seg80 o segment signal output for driving lcd t est table 3. pin description (continued) name i/o description test i test pin this pin is not used for normal operation. test: open note: dummy ? these pins should be opened (floated).
26 com / 80 seg driver & controller for stn lcd KS0093 9 function description system interface KS0093 has two kinds of interface type with mpu: bus mode, serial mode. serial or bus mode is selected by ps pin. in bus mode, 4-bit bus or 8-bit bus is selected by if pin, and 68 series mpu or 80 series mpu is selected by mi pin. table 4 . various kinds of mpu interface according to ps, mi and if ps mi if csb rs rw_wr e_rd db0 ~ ~ db3 db4 ~ ~ db5 db6 db7 8 bit (h) csb rs r/w e db0 ~ db3 db4 ~ db5 db6 db7 68 series (h) 4 bit (l) csb rs r/w e * (1) db4 ~ db5 db6 db7 8 bit (h) csb rs wr rd db0 ~ db3 db4 ~ db5 db6 db7 bus mode (h) 80 series (l) 4 bit (l) csb rs wr rd * db4 ~ db5 db6 db7 serial mode (l) (h)/(l) (2) (h)/(l) csb rs (h)/(l) (h)/(l) * * scl si notes: 1. don?t care (high, low or open) 2. fixed high (v dd ) or low (v ss ) ps: "high" = bus mode, "low" = serial mode mi: "high" = 68-series mpu, "low" = 80-series mpu if: "high" = 8 bit mode, "low" = 4 bit mode (ps: "high") csb: "high" = chip is not selected, "low" = chip is selected rs: "high" = data regist er, "low" = instruction register rw_wr : read / write indicating signal in 68 mode or active low signal for enabling write in 80 mode e_rd: active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode. scl (db6): serial clock input si (db7): serial data input
KS0093 26 com / 80 seg driver & controller for stn lcd 10 interface with mpu in parallel mode (ps = "high") during writing operation, two 8-bit registers, data register (dr) and instruction register (ir), are used. the data register (dr) is used as temporary data storage place for being written into ddram / cgram / iconram and one of these rams is selected by ram address setting instruction. the instruction register (ir) is used only to store instruction code transferred from mpu. to select dr or ir register, rs input pin is used. during reading operation, 8-bit register, output data register (or) is used. the output data register (or) is used as temporary data storage place for being read from ddram / cgram / iconram and one of these rams is selected by ram address setting instruction. after ram address setting, first reading is a dummy cycle in 8-bit bus mode (figure 3, 4). the valid data comes from second reading. in 4-bit bus mode, after ram address setting, first and second reading are dummy cycles (figure 5, 6). the valid data comes from third reading. the dummy read make the address counter (ac) increased by 1. so it is recommended to set address again before writing. the instruction read cycle is not supported and it is regarded as a no operation cycle. in 4-bit bus mode, it is needed to transfer 4-bit data (through db7 ~ db4) by two times. the high order bits (for 8-bit mode db7 ~ db4) are written before the low order bits (for 8-bit mode db3 ~ db0) in write and low order bits (for 8- bit mode db3 ~ db0) are read before the high order bits (for 8-bit mode db7 ~ db4) in read transaction. the db0 ~ db3 pins are floated in this 4-bit bus mode. after resetb resets, KS0093 considers first 4-bit data from mpu as the high order bits. mi csb rs rw_wr e_rd db7 ~ db0 instruction write dummy read data write nop ram read valid data if figure 3. timing diagram of 8-bit parallel bus mode data transfer (68-series mpu mode)
26 com / 80 seg driver & controller for stn lcd KS0093 11 mi csb rs rw_wr e_rd db7 ~ db0 instruction write dummy read data write nop ram read valid data if figure 4. timing diagram of 8-bit parallel bus mode data transfer (80-series mpu mode) mi csb rs rw_wr e_rd db7 ~ db4 instruction write dummy read data write nop ram read upper 4-bit lower 4-bit upper 4-bit lower 4-bit lower 4-bit upper 4-bit if figure 5. timing diagram of 4-bit parallel bus mode data transfer (68-series mpu mode) mi csb rs rw_wr e_rd db7 ~ db4 instruction write dummy read data write nop ram read upper 4-bit lower 4-bit upper 4-bit lower 4-bit lower 4-bit upper 4-bit if figure 6. timing diagram of 4-bit parallel bus mode data transfer (80-series mpu mode)
KS0093 26 com / 80 seg driver & controller for stn lcd 12 interface with mpu in serial mode (ps = "low") when ps input pin is "low", clock synchronized serial interface mode is selected. at this time, five ports, resetb (reset input), scl (db6, synchronizing transfer clock), si (db7, serial input data), rs (register selection input) and csb(chip selection input) are used. by setting csb to "low", KS0093 can receive scl input. if csb is set to "high", KS0093 resets the internal 8-bit shift register and 3-bit counter. serial data is input in the order of "d7, d6, d5, d4, d3, d2, d1, d0" from the serial data input pin (si = db7) at the rising edge of serial clock (scl = db6). at the rising edge of the 8th serial clock, the serial data (d7-d0) is converted into 8 bit bus mode data. the rs input of the dr/ir selection is latched at the rising edge of the 8th serial clock (scl). rs scl (db6) si (db7) csb d7 d6 d5 d4 d3 d2 d1 d0 d7 1 2 3 4 5 6 7 8 9 figure 7. timing diagram of serial data transfer
26 com / 80 seg driver & controller for stn lcd KS0093 13 address counter (ac) address counter (ac) in KS0093 stores ddram/ cgram/ iconram address. after writing into or reading from ddram / cgram / iconram, ac is automatically increased by 1. the address counter is only one and stores the address among ddram / cgram / iconram. display data ram (ddram) ddram stores display data of maximum 64 x 8 bits (max. 64 characters). ddram address is set in the address counter (ac) as a hexadecimal number. 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 20 21 22 23 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 30 31 32 33 com1 ~ com8 com9 ~ com16 hidden line com1 ~ com8 com9 ~ com16 com17 ~ com24 hidden line seg1 seg80 seg1 seg80 1st ch . 16th ch . (1 ) 2 line mode ddram address (2 ) 3 line mode ddram address 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 20 21 22 23 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 30 31 32 33 hidden line figure 8. ddram address character generator rom (cgrom) cgrom has 5 x 8-dot 256 characters. the cg bit of the instruction table selects the 8 characters (00h ~ 07h) of cgrom or cgram.
KS0093 26 com / 80 seg driver & controller for stn lcd 14 table 5. cgrom character code (00)
26 com / 80 seg driver & controller for stn lcd KS0093 15 character generator ram (cgram) cgram has up to 5 x 8-dot 8 characters. by writing font data to cgram, user defined character can be used . cgram can be written regardless of cg bit . table 6. relationship between character code (ddram) and character pattern (cgram) character code (ddram data) dd/cgram address cgram data d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 pattern number 0 0 0 0 0 0 0 0 (00h) 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 1 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 pattern 1 0 0 0 0 0 0 0 1 (01h) 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 pattern 2 0 0 0 0 0 0 1 0 (02h) 1 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 pattern 3 0 0 0 0 0 0 1 1 (03h) 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 - - - 0 1 1 1 0 - - - 1 0 1 0 1 - - - 1 1 0 1 1 - - - 1 0 1 0 1 - - - 0 1 1 1 0 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 pattern 4
KS0093 26 com / 80 seg driver & controller for stn lcd 16 table 6. relationship between character code (ddram) and character pattern (cgram) ( continued ) character code (ddram data) dd/cgram address cgram data d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 pattern number 0 0 0 0 0 1 0 0 (04h) 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 - - - 1 1 0 1 1 - - - 1 0 0 0 1 - - - 0 0 0 0 0 - - - 1 0 0 0 1 - - - 1 1 0 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 pattern 5 0 0 0 0 0 1 0 1 (05h) 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 pattern 6 0 0 0 0 0 1 1 0 (06h) 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 - - - 0 0 1 1 0 pattern 7 0 0 0 0 0 1 1 1 (07h) 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 0 0 0 1 - - - 1 1 0 1 1 - - - 1 0 0 0 1 - - - 0 0 0 0 0 - - - 1 0 0 0 1 - - - 1 1 0 1 1 - - - 1 1 1 1 1 pattern 8 note: "-" - don?t care
26 com / 80 seg driver & controller for stn lcd KS0093 17 segment icon ram (iconram) iconram has segment control data and segment pattern data. comi1 and comi2 are the same signal but the name is different. so the icons on the same seg are displayed at the same time. the number of icons is 80. seg 5 seg 4 seg 3 seg 2 seg 1 comi 2 seg 80 seg 79 seg 78 seg 77 seg 76 comi 1 figure 9. relationship between iconram and icon display table 7. relationship between iconram address and display pattern iconram bits iconram address d7 d6 d5 d4 d3 d2 d1 d0 00h - - - s1 s2 s3 s4 s5 01h - - - s6 s7 s8 s9 s10 02h - - - s11 s12 s13 s14 s15 . . . . . . . . . . . . . . . . . . 0dh - - - s66 s67 s68 s69 s70 0eh - - - s71 s72 s73 s74 s75 0fh - - - s76 s77 s78 s79 s80 note: "-" - don?t care
KS0093 26 com / 80 seg driver & controller for stn lcd 18 low power consumption mode KS0093 provides with sleep mode for saving power consumption during standby period. sleep mode (power save bit on, oscillation bit off) to enter the sleep mode, the power circuit and oscillation circuit should be turned off by using the power save command and the power control command. this mode helps to save power consumption by reducing current to reset level. 1. liquid crystal display output com1 ~ com24, comi1, comi2: v ss level seg1 ~ seg80: v ss level 2. data written in ddram, cgram, iconram and registers are remained as previous value. 3. operation mode is retained the same as it was prior to execution of the sleep mode. all internal circuits are stopped. 4. power circuit and oscillation circuit the built-in power supply circuit and oscillation circuit are turned off by power save command and power control command. lcd driver circuit lcd driver circuit has 26 common and 80 segment signals for driving lcd. data from iconram/ cgram/ cgrom are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. in case of 2-line display mode, com1 ~ com16, comi1 and comi2 have 1/17 duty, and in 3-line mode, com1 ~ com24, comi1 and comi2 have 1/25 duty ratio. seg bi-directional function is selected by dirs input pin, and com shift direction is selected by function set instruction "s" bit. table 8. seg data shift direction dir s pin seg data shift direction low seg1 ? seg2 ? seg3 ....???????? . ............. seg78 ? seg79 ? seg80 high seg80 ? seg79 ? seg78 .......??????? .. ......... seg3 ? seg2 ? seg1 table 9. com data shift direction line mode s com data shift direction 0 (left) com1 ? com2 ......????.... com15 ? com16 ? comi1 (comi2) 2-line mode 1 (right) comi1 (comi2 ) ? com16 ? com15 ....???? . ....... com2 ? com1 0 (left) com1 ? com2 ...????....... com23 ? com24 ? comi1 (comi2) 3-line mode 1 (right) comi1 (comi2 ) ? com24 ? com23 ..... ????? . .. com2 ? com1
26 com / 80 seg driver & controller for stn lcd KS0093 19 instruction description table 10. instruction table instruction rs db7 db6 db5 db4 db3 db2 db1 db0 description return home 0 0 0 0 0 0 0 1 - ddram address is set to 00h from ac and the cursor returns to 00h position the contents of ddram are not changed. double height mode 0 0 0 0 0 1 0 dh2 dh1 double height mode dh2, dh1 = 00: normal display (default) 01: com1 ~ com16 is a double height, com17 ~ com24 is normal 10: 1) 2-line mode : normal display 2) 3-line mode : com1 ~ com8 is normal, com9 ~ com24 is a double height 11: normal display power save 0 0 0 0 0 1 1 os ps power save / oscillation circuit on / off os = 0: oscillator off (default) 1: oscillator on ps = 0: power save off (default) 1: power save on function set 0 0 0 0 1 0 n s cg display line mode n = 0: 2-line display mode (default) 1: 3-line display mode shifting direction of com. s = 0: 1) 2-line mode: com1 -> com16 (default) 2) 3-line mode: com1 -> com24 (default) 1: 1) 2-line mode: com16 -> com1 2) 3-line mode: com24 -> com1 select cgram or cgrom cg = 0: cgrom (default) 1: cgram line shift mode 0 0 0 0 1 1 0 ls2 ls1 determination of the ddram line which is displayed at the first line at lcd ls2, ls1 = 00: ddram line 1 shows at the first line of lcd (default). 01: ddram line 2 shows at the first line of lcd. 10: ddram line 3 shows at the first line of lcd. 11: ddram line 4 shows at the first line of lcd bias control 0 0 0 0 1 1 1 - bs determination of bias bs = 0: 1/5 bias (default ) 1: 1/4 bias power control 0 0 0 1 0 0 vc vr vf lcd power control vc = 0: voltage converter off (default) 1: voltage converter on vr = 0: voltage regulator off (default) 1: voltage regulator on vf = 0: voltage follower off (default) 1: voltage follower on
KS0093 26 com / 80 seg driver & controller for stn lcd 20 table 10. instruction table (continued) instruction rs db7 db6 db5 db4 db3 db2 db1 db0 description display control 0 0 0 1 0 1 c b d cursor / blink / display on / off c = 0: cursor off (default), 1: cursor on b = 0: blink off (default), 1: blink on d = 0: display off (default), 1: display on dd/cgram address set 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 ddram / cgram address range: ddram 00h ~ 3fh cgram 40h ~ 7fh iconram address set 0 0 1 0 ia4 ia3 ia2 ia1 ia0 iconram address, electronic volume and test byte address range: iconram 00h ~ 0fh ev 10h (electronic volume byte), te 11h (test byte) write data 1 d7 d6 d5 d4 d3 d2 d1 d0 write ddram / cgram / iconram read data 1 d7 d6 d5 d4 d3 d2 d1 d0 read ddram / cgram / iconram or registers data (note1) nop 0 0 0 0 0 0 0 0 0 non-operation instruction test 0 0 0 1 1 * * * * don?t use this instruction. note s : 1. "-": don?t care 2. "*": don?t use 3 : instruction execution time depends on the internal process time of KS0093, therefore it is necessary to provide a time larger than one mpu interface cycle time ( tc) between execution of two successive instructions.
26 com / 80 seg driver & controller for stn lcd KS0093 21 return home rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 - return home instruction field makes cursor return home. ddram address is set to 00h from ac and the cursor returns to 00h position. the contents of ddram are not changed. double height mode rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 dh2 dh1 double height mode instruction field selects double height line type. dh2, dh1 = 00: normal display line mode (default) 01: com1 ~ com16 is a double height, com17 ~ com24 is normal 10: 1) 2-line mode: normal display 2) 3-line mode: com1 ~ com8 is normal com9 ~ com24 is a double height 11: normal display figure 10. 3 line normal mode display (dh2, dh1 = 00) figure 11. com1 ~ 16 is a double height line, com17 ~ 24 is normal (dh2, dh1 = 01)
KS0093 26 com / 80 seg driver & controller for stn lcd 22 figure 12. com1 ~ 8 is normal, com9 ~ com24 is a double height line (dh2, dh1 = 10) figure 13. 2-line normal mode display (dh2, dh1 = 00) figure 14. com1 ~ 16 is a double height line (dh2, dh1 = 01)
26 com / 80 seg driver & controller for stn lcd KS0093 23 power save set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 1 os ps power save instruction field is used to control the oscillator and to set or to reset the power save mode. os: oscillator on / off control bit when os = "high", oscillator is turned on when os = "low", oscillator is turned off (default) ps: power save on / off control bit when ps = "high", power save mode is turned on when ps = "low", power save mode is turned off (default) function set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 n s cg n: display line mode instruction field selects 2 line or 3 line display mode when n = "high", 3 line display mode when n = "low", 2 line display mode (default) s: data shift direction of common s sets the shift direction of common display data when s = "high", com right shift when s = "low", com left shift (default) (refer to table 9) cg: cgram enable bit when cg = "high", cgram can be accessed and you can use this ram for eight special character area. (00h - 07h = cgram font display) when cg = "low", cgram is disabled. cgrom (00h~07h) can be accessed and the additional current consumption is saved by using this mode (default). (00h - 07h = cgrom font display)
KS0093 26 com / 80 seg driver & controller for stn lcd 24 line shift mode rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 0 ls2 ls1 line shift mode instruction field selects the dd ram to be displayed in first line. ls2, ls1 = 00: ddram line 1 shows at the first line of lcd (default). 01: ddram line 2 shows at the first line of lcd. 10: ddram line 3 shows at the first line of lcd. 11: ddram line 4 shows at the first line of lcd. dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) lcd ls2, ls1 = 01 dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) lcd ls2, ls1 = 10 dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) lcd ls2, ls1 = 11 dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) lcd ls2, ls1 = 00 figure 15. line shift mode display at 3 line lcd dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) lcd ls2, ls1 = 01 dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) lcd ls2, ls1 = 10 dd ram line4 (30h~3fh) dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) lcd ls2, ls1 = 11 dd ram line1 (00h~0fh) dd ram line2 (10h~1fh) dd ram line3 (20h~2fh) dd ram line4 (30h~3fh) lcd ls2, ls1 = 00 figure 16. line shift mode display at 2 line lcd bias control rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 - bs bias control instruction field sets lcd bias voltages generated internally. this bit is used when the internal voltage follower is on. bs = 0: 1/5 bias (default) 1: 1/4 bias (v2 = v3)
26 com / 80 seg driver & controller for stn lcd KS0093 25 power control set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 vc vr vf power control instruction field sets voltage regulator/ converter/ follower on / off. vc: voltage converter circuit control bit when vc= "high", voltage converter is turned on. when vc = "low", voltage converter is turned off (default). vr: voltage regulator circuit control bit when vr = "high", voltage regulator is turned on. when vr = "low", voltage regulator is turned off (default). vf: voltage follower circuit control bit when vf = "high", voltage follower is turned on. when vf = "low", voltage follower is turned off (default). *note: the oscillation circuit must be turned on for the voltage converter circuit to be active . display control rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 c b d display control instruction field controls cursor / blink / display on / off. c: cursor on / off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display (default). b: cursor blink on / off control bit when c = "high" and b = "high", KS0093 make lcd alternate between inverting display character and normal display character at the cursor position with about a half second. on the contrary, if c = "low" , only a normal character is displayed regardless of "b" flag. when b = "low", blink is off (default). d: display on / off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data are remained in ddram (default).
KS0093 26 com / 80 seg driver & controller for stn lcd 26 table 11. cursor attributes c, b display state 1, 0 1, 1 (blinking mode) 0, 0 0, 1 dd/cg ram address set rs db7 db6 db5 db4 db3 db2 db1 db0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 dd/cg ram address set instruction field sets ddram / cgram address. before writing / reading data into / from the ram, set the address by ram address set instruction. next, when data are written / read in succession, the address is automatically increased by 1. after accessing 7fh, the address of ac is 00h. the address ranges are 00h ~ 7fh.
26 com / 80 seg driver & controller for stn lcd KS0093 27 table 12. dd/cg ram address mapping address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h ddram line 1 (00h ~ 0fh) 10h ddram line 2 (10h ~ 1fh) 20h ddram line 3 (20h ~ 2fh) 30h ddram line 4 (30h ~ 3fh) 40h cgram (pattern 0) cgram (pattern 1) 50h cgram (pattern 2) cgram (pattern 3) 60h cgram (pattern 4) cgram (pattern 5) 70h cgram (pattern 6) cgram (pattern 7) iconram address set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 ia4 ia3 ia2 ia1 ia0 iconram address set instruction field sets iconram / registers address. before writing/reading data into/from the icon ram, set the address by iconram address set instruction. next, when data are written/read in succession, the address is automatically increased by 1. the 5 icons at a time can blink, if c and b bits of the display instructions are enabled. the blink attributes of icon are same as the cursor blink. for accessing dd/cgram, the dd/cgram address set instruction should be set before. after accessing 0fh, the address of iconram address is 00h. the iconram address ranges are 00h ~ 1fh. table 13. iconram address mapping address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h icon ram (00h ~ 0fh) 10h ev te reserved ev: electronic volume register (10h) - default (00000) te: test register (do not use) (11h) when the ev and te registers are written, the address counter (ac) is not increased.
KS0093 26 com / 80 seg driver & controller for stn lcd 28 write data rs db7 db6 db5 db4 db3 db2 db1 db0 1 d7 d6 d5 d4 d3 d2 d1 d0 this instruction field make KS0093 write binary 8-bit data to ddram / cgram / iconram or register. the ram address to be written into is determined by previous dd/cgram address set or iconram address set instruction. after writing operation, the address is automatically increased by 1. read data rs db7 db6 db5 db4 db3 db2 db1 db0 1 d7 d6 d5 d4 d3 d2 d1 d0 ddram / cgram / iconram data read instruction. each ram is selected by address set instruction. and then you can read the ram data. you can get correct ram data from second read transaction. the first read data after setting ram address is dummy data, so the correct ram data come from the second read transaction. after reading operation, the address is increased by 1 automatically.
26 com / 80 seg driver & controller for stn lcd KS0093 29 initializing & power save mode setup hardware reset when resetb pin = "low", KS0093 can be initialized as the following state. (1) control display on / off instruction c = 0: cursor off b = 0: blink off d = 0: display off (2) power save set instruction os = 0: oscillator off ps = 0: power save off (3) power control set instruction vr = 0: voltage regulator off vc = 0: voltage converter off vf = 0: voltage follower off (4) function set instruction n = 0: 2 line display mode s = 0: com left shift cg = 0: cgram is not used. (5) return home address counter = 00h (6) electronic contrast control register: 10h = (0, 0, 0, 0, 0) (7) in case of 4-bit interface mode selection KS0093 considers the first 4-bit data from mpu as the high order bits. *note: if initialization is not done by the resetb pin at application, unknown condition might result. then you can initialize by instruction. reset pulse width t rw 10 m s reset start time t resetb 50ns vdd resetb t resetb t rw figure 17. reset timing
KS0093 26 com / 80 seg driver & controller for stn lcd 30 initializing and power save setup initializing by instruction v dd -v ss power on keep resetb pin = "l" when the power is stable, release the reset state (resetb = " h " ). waiting for 10us or more command input 1. function set (n, s, cg) 2. electronic volume register setup (iconram 10h) 3. power save (ps: power save off, os: osc on) 4. power control (vc, vr, vf are all on) waiting for 20ms or more command input 7. display control (d: on) end of initialization command input 5. ram address set command input 6. data writing (ram clear) (ddram = 20h, cg/iconram = 00h) note: at command 5 and 6, the internal ram should be cleared. to clear ddram, set address at 00h (first ddram) and then write 20h (space character code) 64 times to clear cgram, s et address at 40h (first cgram) and then write 00h (null data) 64 times to clear iconram, set iconram address at 00h (first iconram) and then write 00h (null data) 16 times.
26 com / 80 seg driver & controller for stn lcd KS0093 31 sleep mode set or release by instruction a) sleep mode set b) sleep mode release end of initialization normal operation status (power save is off and oscillator is on.) command input 1. display control (d: off) 2. power save (ps: power save on, os: osc off) 3. power control (vc, vr, vf are all off) enter the sleep mode sleep mode command input 3. display control (d: on) command input 1. power save (ps: power save off, os: osc on) 2. power control (vc, vr, vf are all on) return to normal operation waiting for 20ms or more
KS0093 26 com / 80 seg driver & controller for stn lcd 32 recommendation of power on / off sequence a) power on sequence b) power off sequence power on voltage converter on [vc, vr, vf = 1, 0, 0] voltage regulator on [vc, vr, vf = 1, 1, 0] operation command input waiting for 3 1ms voltage follower on [vc, vr, vf = 1, 1, 1] waiting for 3 1ms operation command input voltage regulator off [vc, vr, vf = 1, 0, 1] voltage follower off [vc, vr, vf = 1, 0, 0] operation command input waiting for 3 50ms voltage converter off [vc, vr, vf = 0, 0, 0] waiting for 3 1ms display off waiting for 3 1ms
26 com / 80 seg driver & controller for stn lcd KS0093 33 lcd driving power supply circuit the power supply circuit produces lcd panel driving voltage at low power consumption. the lcd driving power supply circuit consists of voltage converter, voltage regulator, and voltage follower. it is controlled by power control instruction. table 14 shows how the lcd driving power supply circuit works by power control instruction sets. table 14. power supply control mode set vc vr vf voltage converter voltage regulator voltage follower vout pin vr pin v0, v1, v2, v3, v4 pin 1 1 1 enable enable enable internal voltage output used for voltage adjustment internal voltage output 0 1 1 disable enable enable external voltage input used for voltage adjustment internal voltage output 0 0 1 disable disable enable open open v1 ~ v4: internal voltage output v0: external voltage input 0 0 0 disable disable disable open open v0 ~ v4: external voltage input note: sec recommendation is to use only the case listed above table.
KS0093 26 com / 80 seg driver & controller for stn lcd 34 voltage converter the voltage converter circuit generates positive 4-time voltage of 1.8v that is generated internally. vout is generated from the voltage converter. and this conversion voltage is used in the built-in voltage regulator circuit. this application circuit is same as 3-times dc/dc converter. v ss 1. 8v (internal) vout 4 x 1.8v = 7.2v vdd cap1+ cap1- cap2+ cap2- vout KS0093 v dd + - + - - + figure 18. dc/dc converter output and circuit
26 com / 80 seg driver & controller for stn lcd KS0093 35 voltage regulator the voltage regulator circuit is used to obtain an appropriate lcd panel driving voltage. this voltage is obtained by adjusting resistors ra and rb as shown in equation (1) or (2), and by setting electronic contrast control data bits, see equation (3) or (4). the potential of v0 pin can be adjusted within vout - v ref . v ref is the internal constant voltage source of the chip and this value is 2.0v in the condition v dd 3 2.4v the ref selects which voltage is used for voltage regulator between the external vext and the internal v ref . n voltage regulation by adjusting resistors ra, rb when ref is "low " when ref is "high" rb rb v0 = ( 1 + ) x v ref --- (1) v0 = ( 1 + ) x vext --- (2) ra ra the internal v ref of voltage regulator has the temperature compensation function, and the temperature coefficient is about 0.0%/ c . _ + inside chip gnd ra rb vext v ss vout v0 ref vr v ref figure 19. voltage regulator circuit
KS0093 26 com / 80 seg driver & controller for stn lcd 36 electronic contrast control (32 steps) electronic contrast control data bits is 10h = (c4, c3, c2, c1, c0). voltage regulation is adjusted as 32-contrast step according to the value of electronic contrast control data bits. lcd drive voltage v0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (iconram address 10h). when using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction. when ref = "low " when ref = "high" rb rb v0 = ( 1 + ) x v ev --- (3) v0 = ( 1 + ) x v ev --- (4) ra ra v ev = v ref - n a (n = 0, 1, 2 , ..., 30, 31) v ev = vext - n a (n = 0, 1, 2, ..., 30, 31) a = v ref / 150 a = vext / 150 table 15. electronic contrast control register no. c7 c6 c5 c4 c3 c2 c1 c0 n a a v0 contrast 1 - - - 0 0 0 0 0 0 a (default) 2 - - - 0 0 0 0 1 1 a 3 - - - 0 0 0 1 0 2 a 4 - - - 0 0 0 1 1 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 - - - 1 1 1 1 0 30 a 32 - - - 1 1 1 1 1 31 a maximum . . . . . . . minimum high . . . . . . . low ("-" : d on?t care)
26 com / 80 seg driver & controller for stn lcd KS0093 37 _ + inside chip gnd ra rb vext v ss vout v0 ref vr v ref + v ev - figure 20. electronic contrast control circuit
KS0093 26 com / 80 seg driver & controller for stn lcd 38 voltage generator circuit cap1+ cap1- vdd cap2+ c1: 0.1 ~ 4.7uf c2: 0.1 ~ 4.7 uf vss v4 v3 v2 c1 c1 c1 c2 c2 c2 c2 c2 - + - + gnd gnd v0 v1 rb ra vr vout cap2- vdd figure 21. when built-in power supply is used (vc, vr, vf = 1, 1, 1) cap1+ cap1- vdd cap2+ vss v4 v3 v2 c2 c2 c2 c2 c2 - + gnd gnd v0 v1 rb ra vr vout cap2- cap1+ cap1- vdd cap2+ vss v4 v3 v2 - + gnd v0 v1 vr vout cap2- vdd vss v4 v3 v2 gnd v0 v1 vr gnd cap1+ cap1- cap2+ vout cap2- (vc, vr, vf = 0, 1, 1) (vc, vr, vf = 0, 0, 1) (vc, vr, vf = 0, 0, 0) all capacitor is c2. c2: 0.1 ~ 4.7uf external power supply external power supply external power supply vdd vdd vdd figure 22. when external power supply is used
26 com / 80 seg driver & controller for stn lcd KS0093 39 mpu interface mpu vcc gnd a0 a1-a7 iorq rd wr d0-d7 res decoder rs csb e_rd rw_wr db [0:7] resetb KS0093 ps mi if resetb vdd vss figure 23. parallel interfacing with 8080-series microprocessors mpu vcc gnd a0 a1-a7 vma r/w e d0-d7 res decoder rs csb rw_wr e_rd db[0:7] resetb KS0093 ps mi if resetb vdd vss figure 24. parallel interfacing with 6800-series microprocessors
KS0093 26 com / 80 seg driver & controller for stn lcd 40 mpu vcc gnd port4 port3 port1 port2 res rs csb scl(db6) si(db7) resetb KS0093 mi if e_rd rw_wr ps resetb vdd vss vdd or vss figure 25. clock synchronized serial interfacing with any microprocessors
26 com / 80 seg driver & controller for stn lcd KS0093 41 application information for lcd panel chip bottom & lower view (s bit = "0", dirs = "0") seg80 seg79 seg78 seg77 seg76 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ................................................ com20 com19 com18 com17 com8 com7 com6 com5 com4 com3 com2 com1 comi1 comi2 com24 com23 com22 com21 com16 com15 com14 com13 com12 com11 com10 com9 ........... .... .... ............ ..................... ....... ..................... ........ bottom view chip bottom & upper view (s bit = "1", dirs = "1") seg1 seg2 seg3 seg4 seg5 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 ................................................ com9 com10 com11 com12 com13 com14 com15 com16 com21 com22 com23 com24 comi2 comi1 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 ........... .... .... ............ ..................... ....... ..................... ........ bottom view
KS0093 26 com / 80 seg driver & controller for stn lcd 42 chip top & lower view (s bit = "0", dirs = "1") seg1 seg2 seg3 seg4 seg5 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 ................................................ comi2 com24 com23 com22 com21 com16 com15 com14 com13 com12 com11 com10 com9 com20 com19 com18 com17 com8 com7 com6 com5 com4 com3 com2 com1 comi1 ........... .... .... ............ ..................... ....... ..................... ........ top view chip top & upper view (s bit = "1", dirs = "0") seg80 seg79 seg78 seg77 seg76 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ................................................ comi2 com24 com23 com22 com21 com16 com15 com14 com13 com12 com11 com10 com9 comi1 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 ........... .... .... ............ ..................... ....... ..................... ........ top view
26 com / 80 seg driver & controller for stn lcd KS0093 43 frame frequency 1/17 duty (2-line mode) v0 v1 v4 vss com1 1-line selection period 1 2 16 17 1 2 . . . . . . 16 17 1 2 . . . . . . 16 17 1 2 . . . . . . 16 17 . . . . . . 1 frame 1 frame 1-line selection period = 16 clocks one frame = 16 x 17 x 36.8 m s = 10.0 ms (1 clock = 36.8 m s at f osc =27.2 khz) frame frequency = 1 / 10.0 ms = 100 hz 1/25 duty (3-line mode) v0 v1 v4 vss com1 1-line selection period 1 2 24 25 . . . . . . . . . . . . . 1 2 24 25 1 2 . . . . . . . . . . . . . . . . . . . . . . . 1 frame 1 frame 1-line selection period = 16 clocks one frame = 16 x 25 x 25 m s = 10.0 ms (1 clock = 25 m s at f osc =40 khz) frame frequency = 1 / 10.0 ms = 100 hz
KS0093 26 com / 80 seg driver & controller for stn lcd 44 maximum absolute rat ings table 16. maximum absolute ratings characteristic symbol value unit power supply voltage (1) v dd -0.3 to + 7.0 v power supply voltage (2) vout, v0 -0.3 to + 8.0 v power supply voltage (3) v1, v2, v3, v4 -0.3 to v0 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +85 o c storage temperature t stg -55 to +125 o c notes: 1. all the voltage levels are based on vss = 0v. 2. voltage greater than above may damage the circuit. voltage level: vout 3 v0 3 vdd 3 vss 3. voltage level: v0 3 v1 3 v2 3 v3 3 v4 3 vss
26 com / 80 seg driver & controller for stn lcd KS0093 45 electrical characteristics dc characteristics table 17. dc characteristics (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) item symbol condition min. typ. max. unit operating voltage v dd - 2.4 - 3.6 v i dd1 display operation v lcd = 6v without load no access from mpu - - 80 i dd2 access operation from mpu ( fcyc = 200khz ) - - 500 supply current (v dd = 3v, ta = 25 o c) i dds1 sleep operation without load oscillator off, power save on - - 5 m a v ih - 0.7v dd v dd input voltage (1) v il - v ss 0.3v dd v v oh i oh = -1ma, v dd = 2.4v v dd - 0.4 output voltage v ol i ol = 1ma, v dd = 2.4v 0.4 v input leakage current i iz v in = 0v to v dd -1 - 1 m a output leakage current i oz v in = 0v to v dd -3 3 m a r com io = 50 m a - - 5 r on resistance r seg io = 50 m a - - 10 k w frame frequency (internal osc) f fr v dd = 3v, ta = 25 o c 70 100 130 hz conversion efficiency v ef rl = 95 99 - % voltage converter output voltage v out ta = 25 o c, c = 1 m f 6.9 7.2 7.5 v voltage regulator reference voltage v ref ta = 25 o c 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 - v ss 4.0 - 6.0 v note: 1. resetb p in is schmitt input ( 0.8vdd vih vdd , vss vil 0.2vdd ).
KS0093 26 com / 80 seg driver & controller for stn lcd 46 table 18 . dc characteristics (v dd = 3.6v to 5.5 v, ta = -30 to +85 o c) item symbol condition min. typ. max. unit operating voltage v dd - 3.6 - 5.5 v i dd1 display operation v lcd = 6v without load no access from mpu - - 100 i dd2 access operation from mpu ( fcyc = 200khz ) - - 10 00 supply current (v dd = 5 v, ta = 25 o c) i dds1 sleep operation without load oscillator off, power save on - - 10 m a v ih - 0.7v dd v dd input voltage (1) v il - v ss 0.3v dd v v oh i oh = -1ma, v dd = 4.0 v v dd - 0.4 output voltage v ol i ol = 1ma, v dd = 4.0 v 0.4 v input leakage current i iz v in = 0v to v dd -1 - 1 m a output leakage current i oz v in = 0v to v dd -3 3 m a r com io = 50 m a - - 5 r on resistance r seg io = 50 m a - - 10 k w frame frequency (internal osc) f fr v dd = 5 v, ta = 25 o c 70 100 130 hz conversion efficiency v ef rl = 95 99 - % voltage converter output voltage v out ta = 25 o c, c = 1 m f 6.9 7.2 7.5 v voltage regulator reference voltage v ref ta = 25 o c 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 - v ss 4.0 - 6.0 v note: 1. resetb p in is schmitt input ( 0.8vdd vih vdd , vss vil 0.2vdd ).
26 com / 80 seg driver & controller for stn lcd KS0093 47 ac characteristics parallel write interface (68 mode) (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 450 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - db hold time t h2 50 - - ns (v dd = 3.6v to 5.5v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 350 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 250 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su1 40 - - rs and csb hold time t h1 10 - - db setup time t su2 40 - - db hold time t h2 10 - - ns rs,csb rw_wr e_rd db0~db7 t su1 t h1 t wh t wl t r t su2 t c t h2 t f valid data figure 2 6 . write timing diagram (68-series)
KS0093 26 com / 80 seg driver & controller for stn lcd 48 parallel read interface (68 mode) (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 450 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns (v dd = 3.6v to 5.5v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 450 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns rs ,csb rw_wr e_rd db0~db7 t su t h t wh t wl t r t c t d t dh valid data t f figure 27 . read timing diagram (68-seres)
26 com / 80 seg driver & controller for stn lcd KS0093 49 parallel write interface (80 mode) (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit rw_wr cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 rw_wr pulse width high t wh 150 - - rw_wr pulse width low t wl 450 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - db hold time t h2 50 - - ns (v dd = 3.6v to 5.5v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit rw_wr cycle time t c 350 - - pulse rise / fall time t r ,t f - - 25 rw_wr pulse width high t wh 100 - - rw_wr pulse width low t wl 250 - - rs and csb setup time t su1 40 - - rs and csb hold time t h1 10 - - db setup time t su2 40 - - db hold time t h2 10 - - ns rs ,csb rw_wr e_rd db0~db7 t su1 t h1 t wl t wh t f t su2 t c t h2 t r valid data figure 28 . write timing diagram (80-series)
KS0093 26 com / 80 seg driver & controller for stn lcd 50 parallel read interface (80 mode) (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 150 - - e_rd pulse width low t wl 450 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns (v dd = 3.6v to 5.5v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 150 - - e_rd pulse width low t wl 450 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns rs ,csb rw_wr e_rd db0~db7 t su t h t wl t wh t f t c t d t dh valid data t r figure 29 . read timing diagram (80-series)
26 com / 80 seg driver & controller for stn lcd KS0093 51 clock synchronized serial mode (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min typ max unit scl clock cycle time t c 1000 - - pulse rise / fall time t r ,t f - - 25 scl clock width (high, low) t w 300 - - csb setup time t su1 150 - - csb hold time t h1 700 - - rs data setup time t su2 50 - - rs data hold time t h2 300 - - si data setup time t su3 50 - - si data hold time t h3 50 ns (v dd = 2.4v to 3.6v, ta = -30 to +85 o c) characteristic symbol min typ max unit scl clock cycle time t c 600 - - pulse rise / fall time t r ,t f - - 25 scl clock width (high, low) t w 200 - - csb setup time t su1 100 - - csb hold time t h1 400 - - rs data setup time t su2 50 - - rs data hold time t h2 200 - - si data setup time t su3 40 - - si data hold time t h3 40 ns csb scl rs si tsu3 t su2 tsu1 th3 t h2 t h1 t c t r t w t w t f figure 30. clock synchronized serial interface mode timing diagram

▲Up To Search▲

Price & Availability of KS0093

	To Download KS0093 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .